NanoXmap software transforms the user RTL code and timing constraints into a bit stream downloadable in the eFPGA. It includes its own synthesis and timing analysis in order to optimize how eFPGA features are used and provide timing reports.
The RTL frontend is based on the industry standard Verific parser in order to fficiently support the latest language norms. NanoXmap currently supports Verilog IEEE 1364-1995 / 2001 / 2005.
Timings constraints support a subset of Synopsys SDC language through TCL scripting language.