Key features

Our eFPGA IP includes the following standard features:

  • Real 4 inputs look-up table (LUT) technology to map combinatorial Boolean functions
  • SRAM based
  • Programmable flip-flop (DFF)
  • Fast carry chain structures (CYC)
  • Multiple clock (CLK)
  • Global signals (GS)
  • User I/O

We also offer optional features:

  • Single, dual or true dual port memory
  • Dual port register file
  • Multiplier and accumulator
  • Multiple clock zones

The NX-eFPGA can be programmed through various interfaces. The user can use any combination of them:

  • JTAG Interface
  • Serial SPI Interface
  • 16-bits Parallel Interface
JTAG and SPI interfaces are normally directly accessible through external IO buffers. The fabric JTAG tap controller can be chained with other on die tap controllers if necessary. The Parallel interface can be connected to one SOC internal bus.